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1. Chapter
1: Overview
2.
Capter 2 :
2.1, 2.2 Fabrication
steps
2.3.1 ?2.3.4 Simple
transistor model and tub tie and latch up
current, voltage and gate
capacitance
2.4
wires and vias
2.5-2.6
Design rules and stick diagram
Chapter
3
3.1, 3.2
Combination logic
1.Chaper
1:
Overview
2. Chaper
2 :
2.1,
2.2
Fabrication steps
2.3.1
?2.3.4 Simple
transistor model and tub tie and latch up
current,
voltage and gate capacitance
2.4
wires and vias
2.5-2.6
Design rules and stick diagram
Chapter 3
3.1,
3.2
Combination logic
3.3
?3.6
Noise margin, delay, power consumption
driving large load, switch logic,
Peseudo-nMOS, Domino, DCVS
4.Chaper
5: 5.1-5.2
latch and flip-flop
5.4.1 FSM design & sequential logic
Notes:
Scale, yield, routing, simulation, VHDL/Verilog, adder, memory, FPGA
(Sections 4.1-4.3, 6.7, 8.2)